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features floating channel designed for bootstrap operation fully operational to +600 v tolerant to negative transient voltage, dv/dt immune gate drive supply range from 10 v to 20 v undervoltage lockout for both channels 3.3 v logic compatible separate logic supply range from 3.3 v to 20 v logic and power ground +/- 5 v offset cmos schmitt-triggered inputs with pull-down cycle by cycle edge-triggered shutdown logic matched propagation delay for both channels outputs in phase with inputs product summary v offset 600 v max. i o +/- 200 ma / 440 ma v out 10 v - 20 v t on/off (typ.) 135 ns & 105 ns delay matching 30 ns www.irf.com 1 data sheet no. pd60251 irs2112 ( - 1, - 2,s ) pbf description the irs2112 is a high voltage, high speed power m osfet and igbt driver with independent high- and low-side referenced output channels. proprietary hvic and latch immune cmos technologies enable rug- gedized monolithic construction. logic inputs are com- patible with standard cmos or lsttl outputs, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high-side configuration which operates up to 600 v. (refer to lead assignments for correct pin configuration). this diagram shows electrical connections only. please refer to our application notes and designtips for proper circuit board layout. typical connection hin up to 600 v to load v dd v b v s ho lo com hin lin v ss sd v cc lin v dd sd v ss v cc packages 1 6 - l e a d s o ic i r s 2 1 1 2s 1 4 - l e a d p d ip (w/o lead 4) i r s 2 1 12-1 14-lead pdip i r s 2 1 12 16-lead pdip (w/o leads 4 & 5) irs2112-2 high and low side driver ? rohs compliant
irs2112(-1,-2,s)pbf www.irf.com 2 note 1: logic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). note 2: when v dd < 5 v, the minimum v ss offset is limited to -v dd . symbol definition min. max. units v b high-side floating supply voltage -0.3 625 v s high-side floating supply offset voltage v b - 25 v b + 0.3 v ho high-side floating output voltage v s - 0.3 v b + 0.3 v cc low-side fixed supply voltage -0.3 25 v lo low-side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (fig. 2) ? 50 v/ns p d package power dissipation @ t a +25 c (14 lead dip) ? 1.6 (16 lead soic) ? 1.25 r th ja thermal resistance, junction to ambient (14 lead dip) ? 75 (16 lead soic) ? 100 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figs. 28 through 35. c/w w v c symbol definition min. max. units v b high-side floating supply absolute voltage v s + 10 v s + 20 v s high-side floating supply offset voltage note 1 600 v ho high-side floating output voltage v s v b v cc low-side fixed supply voltage 10 20 v lo low-side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 2) 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15 v differential. typical ratings at other bias conditions are shown in figs. 36 and 37. v pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 3 irs2112(-1,-2,s)pbf symbol definition min. typ.max.unitstest conditions t on turn-on propagation delay vs = 0 v t off turn-off propagation delay t sd shutdown propagation delay ? 130 160 t r turn-on rise time t f turn-off fall time mt delay matching, hs & ls turn-on/off ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15 v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in fig. 3. symbol definition min.typ. max.unitstest conditions v ih logic ?1? input voltage 9.5 ? ? v il logic ?0? input voltage ? ? 6.0 v oh high level output voltage, v bias - v o ? 0.05 0.2 v ol low level output voltage, v o ? 0.02 0.1 i lk offset supply leakage current ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 25 100 i qcc quiescent v cc supply current ? 80 180 i qdd quiescent v dd supply current ? 2 .0 30 i in+ logic ?1? input bias current ? 20 40 v in = v dd i in- logic ?0? input bias current ? ? 1.0 v in = 0 v v bsuv+ v bs supply undervoltage positive going 7.4 8.5 9.6 threshold v bsuv- v bs supply undervoltage negative going 7.0 8.1 9.2 threshold v ccuv+ v cc supply undervoltage positive going 7.6 8.6 9.6 threshold v ccuv- v cc supply undervoltage negative going 7.2 8.2 9.2 threshold i o+ output high short circuit pulsed current 200 290 ? v o = 0 v, v in = v dd pw 10 s i o- output low short circuit pulsed current 420 600 ? v o = 15 v, v in = 0 v pw 10 s static electrical characteristics v bias (v cc , v bs , v dd ) = 15 v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin, and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. a v ma v v in = 0 v or v dd i o = 2 ma v s = 600 v pdf created with pdffactory trial version www.pdffactory.com ? 135 180 ? 130 160 ? 75 130 ? 35 65 ? ? 30
irs2112(-1,-2,s)pbf www.irf.com 4 functional block diagram sd lin v dd pulse gen r s q v ss uv detect delay hv level shift pulse filter uv detect v dd /v cc level shift v dd /v cc level shift r s q r s r q hin com ho v s v cc lo v b lead definitions symbol description v dd logic supply hin logic input for high-side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low-side gate driver output (lo), in phase v ss logic ground v b high-side floating supply ho high-side gate drive output v s high-side floating supply return v cc low-side supply lo low-side gate drive output com low-side return pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 5 irs2112(-1,-2,s)pbf lead assignments part number 14 lead pdip irs2112 16 lead soic (wide body) irs2112s 14 lead pdip w/o lead 4 irs2112-1 16 lead pdip w/o leads 4 & 5 irs2112-2
irs2112(-1,-2,s)pbf www.irf.com 6 figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% hin lin ho 50% 50% 10% lo 90% mt ho lo mt sd t sd ho lo 50% 90% hv = 10 v to 600 v v cc = 15 v 10 m f 0.1 m f 10 k f6 0.1 m f 100 m f 200 m h 10 k f6 1 2 13 12 11 10 7 5 6 3 9 ho output monitor 10 k f6 irf820 dv s ct hv = 10 v to 600 v v cc = 15 v 10 m f 0.1 m f 0.1 m f 10 m f 10 m f 15 v 1 2 13 12 11 10 7 5 6 3 9 ho lo c l c l (0 v to 600 v) v s - + v b hin lin sd hin lin ho lo sd pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 7 irs2112(-1,-2,s)pbf figure 7b. turn-on propagation delay time vs. v cc /v bs supply voltage figure 7c. turn-on propagation delay time vs. v dd supply voltage figure 8b. turn-off propagation delay time vs. v cc /v bs supply voltage figure 8c. turn-off propagation delay time vs. v dd supply voltage 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature( o c) t u r n - on delay tim e ( ns) . typ. max. figure 7a. turn-on propagation delay time vs. temperature 0 50 100 150 200 250 10 12 14 16 18 20 v cc / v bs supply voltage (v) t u r n - on delay tim e ( ns ) . typ. max max. typ. 0 100 200 300 400 0 2 4 6 8 10 12 14 16 18 20 v dd supply voltage (v) t u r n - o n d e l a y t i m e ( n s ) . typ. max. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature( o c) t u r n - o f f t i m e ( n s ) figure 8a. turn-off propagation delay time vs. temperature max. typ. 0 50 100 150 200 250 10 12 14 16 18 20 v cc /v bs supply voltage (v) tu rn- o ff t im e (ns ) typ. max. 0 100 200 300 400 0 2 4 6 8 10 12 14 16 18 20 v dd supply voltage (v) tur n-o ff delay tim e ( ns ) pdf created with pdffactory trial version www.pdffactory.com
irs2112(-1,-2,s)pbf www.irf.com 8 figure 10a. turn-on rise time vs. temperature figure 10b. turn-on rise time vs. voltage figure 11a. turn-off fall time vs. temperature figure 9b. shutdown delay time vs. v cc /v bs supply voltage figure 9c. shutdown time vs. v dd supply voltage typ. max. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature( o c) s h u t d o w n d e l a y t i m e ( n s ) figure 9a. shutdown delay time vs. temperature max. typ. 0 50 100 150 200 250 10 12 14 16 18 20 v cc /v bs supply voltage (v) sh utd ow n d ela y t ime ( n s ) typ. max. 0 100 200 300 400 0 2 4 6 8 10 12 14 16 18 20 v dd supply voltage (v) s h u t d o w n d e l a y t i m e ( n s ) typ. max. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o n r i s e t i m e ( n s ) . typ max 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) t u r n - o n r i s e t i m e ( n s ) . typ. max. 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 temperature ( o c) t ur n- o ff f al l t im e ( ns ) pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 9 irs2112(-1,-2,s)pbf figure 11b. turn-off fall time vs. supply voltage figure 12a. logic ?i? input threshold vs. temperature 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 l o g i c " 1 " i n p u t t h r e s h o l d ( v ) temperature (c) min. 0 3 6 9 1 2 1 5 2.5 5 7.5 10 12.5 15 17.5 20 l o g i c " 1 " i n p u t t r e s h o l d ( v ) v dd logic supply voltage (v) figure 12b. logic ?i? input threshold vs. voltage min. 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 l o g i c " 0 " i n p u t t h r e s h o l d ( v ) temperature (c) figure 13a. logic ?0? input threshold vs. temperature max. 0 3 6 9 1 2 1 5 2.5 5 7.5 10 12.5 15 17.5 20 l o g i c " 0 " i n p u t t r e s h o l d ( v ) v dd logic supply voltage (v) figure 13b. logic ?0? input threshold vs. voltage max. figure 14a. high level output voltage vs. temperature (i o = 2 ma) typ max 0 25 50 75 100 125 10 12 14 16 18 20 v bias supply voltage (v) tur n- o ff fal l tim e ( ns) max. 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature ( o c) h i g h l e v e l o u t p u t v o l t a g e ( v ) pdf created with pdffactory trial version www.pdffactory.com
irs2112 ( - 1, - 2,s ) pbf www.irf.com 10 figure 14b. high level output voltage vs. supply voltage (i o = 2 ma) figure 15a. low level output voltage vs. temperature (i o = 2 ma) figure 15b. low level output voltage vs. supply voltage ( i o = 2 ma) figure 17a. v bs supply current vs. temperature max 0.0 0.2 0.4 0.6 0.8 1.0 10 12 14 16 18 20 v bais supply voltage (v) h i g h l e v e l o u t p u t v o l t a g e ( v ) max 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature ( o c) l o w l e v e l o u t p u t v o l t a g e ( v ) max 0.0 0.2 0.4 0.6 0.8 1.0 10 12 14 16 18 20 v bais supply voltage (v) l o w l e v e l o u t p u t v o l t a g e ( v ) figure 16b. v bs supply current vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) max. typ. max. typ. 0 50 100 150 200 -50 -25 0 25 50 75 100 125 temperature ( o c) figure 16a. v bs supply current vs. temperature typ. max. 0 50 100 150 200 10 12 14 16 18 20 v bs supply voltage (v) v bs supply current ( m a) v bs supply current ( m a) v bs supply current ( m a)
www.irf.com 11 irs2112(-1,-2,s)pbf figure 20a. logic ?i? input current vs. temperature figure 17b. v bs supply current vs. voltage 0 20 40 60 80 100 10 12 14 16 18 20 v bs supply current ( m a) max. typ. v bs floating supply voltage (v) 0 50 100 150 200 250 300 -50 -25 0 25 50 75 100 125 v cc supply current ( m a) temperature (c) max. typ. figure 18a. v cc supply current vs. temperature figure 18b. v cc supply current vs. voltage 0 50 100 150 200 250 300 10 12 14 16 18 20 v cc supply current ( m a ) v cc fixed supply voltage (v) max. typ. 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 v dd supply current ( m a) temperature (c) max. typ. figure 19a. v dd supply current vs. temperature figure 19b. v dd supply current vs. v dd voltage 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 v d d s u p p ly c u r r e n t ( m a ) v dd logic supply voltage (v) max. typ. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 l o g i c " 1 " i n p u t b i a s c u r r e n t ( m a ) temperature (c) max. typ. pdf created with pdffactory trial version www.pdffactory.com
irs2112 ( - 1, - 2,s ) pbf www.irf.com 12 figure 20b. logic ?1? input current vs. v dd voltage 0 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 20 v dd logic supply voltage (v) current (ua) max. typ. figure 22. v bs undervoltage (+) vs. temperature max. typ. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 v b s u n d e r v o l t a g e l o c k o u t - ( v ) temperature (c) figure 23. v bs undervoltage (-) vs. temperature max. typ. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 v cc undervoltage lockout +(v) temperature max. typ. min. figure 24. v cc undervoltage (-) vs. temperature 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 v bs u n d e r v o l t a g e l o c k o u t + ( v ) temperature (c) ( o c ) max 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature (c) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) figure 21a. logic "0" input bias current vs. temperature max 0 1 2 3 4 5 6 10 12 14 16 18 20 supply voltage (v) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) figure 21b. logic "0" input bias current vs. voltage logic "1" input bias
www.irf.com 13 irs2112(-1,-2,s)pbf 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 v cc undervoltage lockout - (v) temperature (c) figure 25. v cc undervoltage (-) vs. temperature max. typ. min. figure 26a. output source current vs. temperature figure 26b. output source current vs. supply voltage figure 27b. output sink current vs. supply voltage min. typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t pu t s o ur c e c u r r e n t ( m a ) min. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) o u t p u t so u r c e c u r r e n t ( m a ) min. typ. 0 150 300 450 600 750 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t pu t s ink c u r r e n t ( ma ) figure 27a. output sink current vs. temperature min. typ. 0 150 300 450 600 750 10 12 14 16 18 20 v bias supply voltage (v) o u t p u t s i nk cu r r en t ( m a ) pdf created with pdffactory trial version www.pdffactory.com
irs2112(-1,-2,s)pbf www.irf.com 14 figure 28. irs2112 t j vs. frequency (irfbc20) r gate = 33 w , v cc = 15 v figure 29. irs2112 t j vs. frequency (irfbc30) r gate = 22 w , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v figure 33. irs2112s t j vs. frequency (irfbc30) r gate = 22 w , v cc = 15 v figure 32. irs2112s t j vs. frequency (irfbc20) r gate = 33 w , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v figure 31. irs2112 t j vs. frequency (irfpe50) r gate = 10 w , v cc = 15 v figure 30. irs2112 t j vs. frequency (irfbc40) r gate = 15 w , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 15 irs2112(-1,-2,s)pbf figure 34. irs2112s t j vs. frequency (irfbc40) r gate = 15 w , v cc = 15 v figure 35. irs2112s t j vs. frequency (irfpe50) r gate = 10 w , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v 140 v 10 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320 v140 v10 v figure 36. maximum v s negative offset vs. v bs supply voltage figure 37. maximum v ss positive offset vs. v cc supply voltage -15.0 -12.0 -9.0 -6.0 -3.0 0.0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v) typ. 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply voltage (v) v ss logic supply offset voltage (v) typ. pdf created with pdffactory trial version www.pdffactory.com
irs2112(-1,-2,s)pbf www.irf.com 16 01-6010 01-3002 03 (ms-001ac) 14-lead pdip case outline 14-lead pdip w/o lead 4 01-6010 01-3008 02 (ms-001ac) pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 17 irs2112(-1,-2,s)pbf 16-lead soic (wide body) 01 6015 01-3014 03 (ms-013aa) 16 lead pdip w/o leads 4 & 5 01-6015 01-3010 02 pdf created with pdffactory trial version www.pdffactory.com
irs2112(-1,-2,s)pbf www.irf.com 18 carrier tape dimension for 16soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 10.80 11.00 0.425 0.433 f 10.60 10.80 0.417 0.425 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h note : controlling dimension in mm loaded tape feed direction a h f e g d b c tape & reel 16-lead soic pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 19 irs2112(-1,-2,s)pbf leadfree part marking information order information 14-lead pdip irs2112pbf 14-lead pdip irs2112-1pbf 16-lead pdip irs2112-2pbf 16-lead soic irs2112spbf 16-lead soic tape & reel irs2112strpbf lead free released non-lead free released part number date code irsxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code the soic-16 is msl3 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 11/27/2006 pdf created with pdffactory trial version www.pdffactory.com

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